1. Field of the Invention
This present invention relates to a semiconductor memory device and a manufacturing method thereof, for example, a nonvolatile semiconductor memory device and its manufacturing method that are suitable for high integrality.
2. Description of the Related Art
We will explain about a structure of a conventional nonvolatile semiconductor memory device. FIG. 38 shows a schematic top view of the conventional nonvolatile semiconductor memory device. FIG. 38a shows a region where memory cells that are MOS transistors having a floating gate respectively are arranged in an array form, hereinafter, referred to a memory cell region. FIG. 38b shows a region where MOS transistors that have no floating gate and control the memory cells are arranged, hereinafter, referred to a peripheral region.
Generally, the memory cell region is formed with high density in order to achieve high capacity and integrity. Therefore, the peripheral region referred by FIG. 38b is formed with lower density compared to the memory cell region.
As shown in FIG. 38a, in the memory cell region, element regions 161 where memory cells are formed and element isolation regions 162 that separate each of the element regions 161 with each other are arranged in a stripe shape. One of the element regions 161 includes a plurality of memory cells in a horizontal direction of the FIG. 38a. In a direction perpendicular to the element regions 161, gate connection lines 163 that connect each control gates (not shown) with each other are arranged in a stripe shape.
Floating gates (not shown) are arranged in each of intersected portions between the gate connection line 163 and the element region 161. A semiconductor substrate under each of the floating gates works as channel region (not shown). Diffusion layers (not shown) that are used as source or drain regions are arranged in the semiconductor substrate adjacent to the channel region. Each of contact layers 164 is electrically connected to one of the diffusion layers.
FIG. 38b shows a peripheral region. As shown in FIG. 38b, element regions 171 and element isolation regions 172 that electrically separate each of the element regions 161 with each other are arranged in a stripe shape. In a direction perpendicular to the element regions 171, gate connection lines 173 that connect each of gate electrodes (not shown) with each other are arranged in a stripe shape.
Gate electrode regions (not shown) are arranged in each of intersected portions between the gate connection line 173 and the element region 171. A semiconductor substrate under each of the gate electrode regions works as channel region (not shown). Diffusion layers (not shown) that are used as source or drain regions are arranged in the semiconductor substrate adjacent to the channel region. Each of contact layers 174 is electrically connected to one of the diffusion layers. Each of contact layers 175 is electrically connected to one of the diffusion layers. In the peripheral region shown in FIG. 38b, MOS transistors are arranged in lower integrity than that of the memory cell region shown in FIG. 38a. 
Hereinafter, steps of manufacturing such as the nonvolatile memory device will be shown schematically with reference to FIG. 39 to FIG. 42. Each of FIG. 39a to FIG. 42a shows a cross sectional view similar to an A-Aa cross sectional view shown in FIG. 38a. Each of FIG. 39b to FIG. 42b shows a cross sectional view similar to a B-Ba cross sectional view shown in FIG. 38a. Each of FIG. 39c to FIG. 42c shows a cross sectional view similar to a C-Ca cross sectional view shown in FIG. 38b. Also, same reference numbers will be commonly fed to same portions over FIG. 39 to FIG. 42.
As shown in FIG. 39, a gate insulation film 102 is formed on a semiconductor substrate 101. A poly crystalline silicon layer 103 formed on the gate insulation film 102 and a poly crystalline silicon layer 107 formed thereon are used as a floating gate in the memory cell region (See FIGS. 39a and 39b) and are used as a part of the gate electrode in the peripheral region (See FIG. 39c).
A reference number 108 in FIGS. 39a and 39b shows a second gate insulating film which is, for instance, comprised of an ONO (Oxide-Nitride-Oxide) layer. A poly crystalline silicon layer 109 and a WSi (Tungsten Silicide) layer 110 are formed on the second gate insulating film. The poly crystalline silicon layer 109 is used as the gate connection line 163. Silicon oxide layers 111 and 112 are formed on the WSi layer 110. The WSi layer 110 is also used as a part of the control gate electrode in the memory cell region.
As shown in FIG. 39c, the WSi layer 110 is used as a part of the gate electrode in the peripheral region. It should be noted that, as shown in FIG. 39, a silicon oxide layer 112 is formed above upper surfaces of the gate electrode in the memory cell region and the peripheral region, and on side surfaces of the gate electrode in the memory cell region and the peripheral region at this stage.
As shown in FIG. 40, a silicon nitride layer 113 with 40 nm in thickness is formed on the silicon oxide layer 112 by using a low pressure CVD (Chemical Vapor Deposition) method. A BPSG (Boron phosphor Silicate Glass) layer 114 with 400 nm in thickness is formed on the silicon nitride layer 113 in order to fulfill intervals between the gate electrodes by using a normal pressure CVD method. After that, the BPSG layer 114 is reflowed by adding heat with 850 degrees centigrade and nitrogen atmosphere. Moreover, a BPSG layer 115 with 300 nm in thickness is formed on the BPSG layer 114. After that, the BPSG layer 115 is reflowed by adding heat with 850 degrees centigrade and nitrogen atmosphere. Simultaneously, dopants in the diffusion layer 129 are diffused.
As shown in FIG. 41, by using a CMP (Chemical Mechanical Polishing) method, parts of the BPSG layer 114 and 115 are removed so as to expose upper surfaces of the silicon nitride layer 113. A silicon oxide layer 116 with 100 nm in thickness is formed by using a plasma CVD method. And then, a photo resist layer (not shown) is formed on the silicon oxide layer 116 and is processed into a desirable pattern by using a photolithography technique. Parts of the silicon oxide layer 116, the BPSG layer 114, and 115 are removed by using the patterned resist layer as a mask and RIE (Reactive Ion Etching) method, thereby forming a first contact hole 117a. 
The patterned photo resist layer is removed. And then, by using RIE (Reactive Ion Etching) method and the patterned silicon oxide layer 116 as a mask, the silicon nitride layer 113 and the gate insulating layer 102 that are located under a bottom surface of the contact hole 117a are removed so as to expose an upper surface of the semiconductor substrate 101. Formations that are formed on a side surface of the contact hole 117a at the RIE method are removed. After that, by using a CVD method, a tungsten layer 117 with 400 nm in thickness is formed so as to cover the silicon oxide layer 116 and fulfill the contact hole 117a. 
As shown in FIG. 42, by using a CMP method, parts of the tungsten layer 117 and the silicon oxide layer 116 are removed so as to expose upper surfaces of the silicon nitride layer 113 in order to flatten and identify heights of an upper surface of the tungsten layer 117 and the silicon nitride layer 113. A silicon oxide layer 118 with 450 nm in thickness is formed on the silicon nitride layer 113 and the tungsten layer 117 by using a plasma CVD method. A photo resist layer (not shown) is then formed on the silicon oxide layer 118 and patterned into a predetermined pattern by using a photo lithography technique. By using a RIE method and the patterned resist layer as a mask, a second contact hole 119a is formed so as to reach upper surfaces of the tungsten layer 117 that is formed in the contact hole 117a (FIG. 42b) and the WSi layer 110 that will be used as a gate electrode (FIG. 42c).
The patterned photo resist layer is removed. And then, a second tungsten layer 119 with 250 nm in thickness is formed so as to cover an upper surface of the silicon oxide layer 118 and fulfill the second contact hole 119a. Steps that are going to be done afterward are omitted.
As stated above, the contact layer (the contact layers 164 in FIG. 38a or the tungsten layer 117, and the second tungsten layer 119 in FIG. 42b) that reaches a source or drain region of the memory cell is formed in the memory cell region. Also, the contact layers that reach a source or drain region of the peripheral MOS transistor (the contact layers 174 in FIG. 38b, and the tungsten layer 117 and the second tungsten layer 119 in FIG. 42c) and reach a gate electrode of the peripheral MOS transistor (the contact layers 175 in FIG. 38b, and the second tungsten layer 119 in FIG. 42c) are formed in the peripheral region.
As shown in FIGS. 38 and 42, a pattern density of the contact layers in a region where the contact layers are formed depends on whether the contact layer is connected to a source/drain region or a gate electrode. Also, as stated above, forming the contact layers is done by forming at least two contact holes and then fulfill such conductive layers as the tungsten layers in each of the at least two contact holes.
It is necessary that not only parts of the silicon oxide layers 118, 112, and 111 but also a part of the silicon nitride layer 113 are removed in order to form the second contact hole 119a. Therefore, in this case, it is not desirable that parts of the silicon oxide layer and the silicon nitride layer are removed by using a RIE method with a sufficient etching ratio between the silicon oxide layer and the silicon nitride layer. If the silicon oxide layer and the silicon nitride layer were removed under the condition, as shown in FIG. 43a, the silicon nitride layer that is located in the contact hole 119a could not be removed totally and a part of the silicon nitride layer in the contact hole 119a could remain. Therefore, a connection defect between the second tungsten layer 119 and the WSi layer 110 (the gate electrode) may happen.
If the silicon oxide layer and the silicon nitride layer were removed without a sufficient etching ratio between the silicon oxide layer and the silicon nitride layer, the connection defect between the second tungsten layer 119 and the WSi layer 110 that is stated above could be avoided. However, as shown in FIG. 43b, it may happen that the second contact holes 119a in a high density region (for instance, a memory cell region) are formed not to coincide with the contact hole 117a. 
In this case, when the contact hole 119a is formed by using an etching technique, it is difficult to make a position of a bottom surface of the contact hole 119a stopped at a position of an upper surface of the tungsten layer 117. For this reason, portions of the insulating layer 114, the silicon oxide layers 111, 112, and the silicon nitride layer 113 could be removed, thereby exposing a side surface of the WSi layer 110 and shorting between the second tungsten layer 110 that is exposed in the contact hole 119a and the WSi layer 110 that is used as a control gate.
Actually, we can not perfectly avoid a position difference between the bottom surface of the contact hole 119a and the upper surface of the tungsten layer 117. As the integrality of the memory cells and the peripheral transistors progressed, specifically, the problem stated above tends to happen in the memory cell region that is formed with a high integrality